1. Field of the Invention
The present invention relates generally to CMOS phase and frequency detector (PFD) circuits used in the locking of phase locked loops (PLL) and delay locked loops (DLL). This invention relates more specifically to very high speed CMOS logic implementations of such circuits.
2. Description of the Related Art
High speed phase locked loops (PLL) are used in modern communication systems for many purposes, including clock generation and data recovery and retiming. Typically, the input signal for the reference input of a PLL is a differential signal where the crossing of the true and complement signals represents the clock transition. However, phase and frequency detector circuits (PFD) used for clock multiplication and generation are typically single-ended circuits. When a differential reference signal is provided to a PFD, either a differential to single phase conversion is done or only one phase of the differential signal is used for the PFD circuit.
It is well known that differential CMOS circuits, especially current mode logic circuits (CML), are generally faster and generate lower noise than single-ended CMOS circuits, but since PFD circuits are single-ended circuits they cannot take advantage of the benefits of differential signaling.
With reference to FIG. 1, a known PFD architecture is composed of two single-ended, edge triggered D-flip-flops 1 and 3 with asynchronous reset and one AND gate 5. There exists a complementary but similar architecture using an OR gate. D-flip-flops 1 and 3 are conventionally implemented with CMOS logic circuits, although other implementations with other single-ended logic families using NFETs and PFETS in non-complementary configurations are known.